The present invention relates to a semiconductor memory apparatus, and more particularly, to structure and operating method of the semiconductor memory apparatus for solving a problem occurred in a unit cell because of high-integration.
In a system constituted with a plurality of semiconductor devices, a semiconductor memory apparatus is configured to store data generated or processed therein. For example, if a request from a data processor such as a central processing unit (CPU) is received, the semiconductor memory apparatus outputs data to the data processor from unit cells therein or stores data processed by the data processor to the unit cells, according to an address transmitted with the request.
Recently, data storage capacity of the semiconductor memory apparatus is increased, but the size of the semiconductor memory apparatus is not increased proportionally. Thus, each of plural unit cells included in the semiconductor memory apparatus is dwindled, and the sizes of various components and elements for read or write operations are also reduced. Accordingly, components and elements duplicated unnecessarily in the semiconductor memory apparatus, such as transistors or wires, are combined or merged to lesson the area occupied by each component. Particularly, the reduction of the size of unit cells included in the semiconductor memory apparatus affects improvement of integration because the unit cells occupy one of the largest areas therein.
FIG. 1 is a circuit diagram illustrating a unit cell included in a conventional semiconductor memory apparatus. In particular, FIG. 1 shows a Dynamic Random Access Memory (DRAM) which is a type of volatile memory device configured to retain data while a power source is supplied.
As shown, the unit cell comprises a transistor serving as a switch and a capacitor functioning as a data storage unit. One of the source/drain regions of the transistor is connected to a bit line BL, and the other of source/drain regions is connected to a storage node (SN). A gate of the transistor is connected to a word line WL, and a body of the transistor is connected to a body voltage VBB.
When a high voltage VPP is supplied to the word line, the unit cell is activated to transmit charges corresponding to a logic level of data “1” or “0” through the bit line and to store the charges in the capacitor. A driving voltage supplied to the word line to activate the unit cell may include a power voltage VDD or a core voltage VCORE which has a lower level than the high voltage VPP depending on specifications of the semiconductor memory apparatus. Nevertheless the high voltage is generally supplied on the word line for turning on the transistor. When a voltage level supplied to the gate of the transistor is higher, transmitted data through the transistor may be freer from a threshold voltage of the transistor and, as a result, distortion or degradation of data is prevented.
As the voltage corresponding to the logic level of data “1” or “0” transmitted onto the storage node SN of the unit cell, a core voltage or a ground voltage (0V) is generally used. Also, a half of core voltage 0.5*VCORE is supplied to the other side of the capacitor as a plate voltage. In this case, a potential difference of +0.5*VCORE is maintained between both ends of the capacitor when the data “1” is delivered to the unit cell, and a potential difference of 0.5*VCORE is kept between both the ends of the capacitor when the data “0” is transmitted.
After the data “1” is delivered to the capacitor, charges that are temporarily stored in the storage node are dissipated, i.e., amount of the charges are reduced, because of several leakage currents that are generated in junction of the storage nodes or instinctive characteristics of the capacitor as time goes by. In order to prevent the reduction of charges, numerous methods for increasing a capacitance (Cs) of the capacitor included in the unit cell have been suggested so that more charges may be stored in the storage node and for a longer time after the charges are inputted to the unit cell through the write operation. For example, a prior insulating film of the capacitor, e.g., an oxide film, is replaced with an advanced insulating film which has a larger dielectric constant such as a nitrified oxide film and a high dielectric film. Otherwise, the capacitor having a two-dimensional structure is changed to have a three-dimensional cylinder structure or a trench structure, thereby increasing the surface of both electrodes of the capacitor.
As the design rule is reduced, the plane area where a capacitor can be formed is reduced. Thus, in order to form a capacitor having a higher height in a narrow area, a material having a high aspect ratio is used. Yet, as the plane area for the capacitor is continuously reduced, there is a limit to increasing the height or depth of the capacitor.
As it is difficult to develop materials for forming the insulating film in the capacitor, it remains difficult to secure capacitance of the capacitor of more than 25 fF which is suitable for the semiconductor memory apparatus that reads or writes data as well as performs a refresh operation to prevent distortion of the data under the design rule of less than 50 nm. Moreover, as a junction resistance of the storage node in the unit cell and a turn-on resistance of the transistor increase under the reduction of the design rule, performing the read and write operations become more difficult.
FIG. 2 is a circuit diagram illustrating a unit cell of a floating body transistor semiconductor memory apparatus.
As shown, the unit cell includes one transistor without any capacitor used to store data. A body of the one transistor included in the unit cell is floated, not connected to the body voltage. It's called a floating body (FB) transistor. In a write mode of the unit cell, a voltage level supplied on the word line coupled to a gate of the FB transistor is reduced by ½ or ⅓ of the voltage level corresponding to the logic level of data ‘1’, which may be supplied to one source/drain region of the FB transistor through the bit line, in order to generate a lot of hot carriers. At this time, a source line (SL) which is the other source/drain region of the FB transistor is connected to a ground voltage (GND).
When the data “1” is delivered, a large amount of hot carriers are generated in a junction region between the FB transistor and the bit lines BL during the write mode. Then, electrons are slipped out into the bit line BL but holes remain in the floating body FB. Otherwise, when the data “0” is transmitted, the hot carriers are not generated in the junction region, so that any hole does not remain in the floating body FB.
On the read mode, the holes kept in the floating body lower a threshold voltage of the transistor of the unit cell; and, as a result, amount of a current flowing through a channel of the transistor increases. That is, the amount of the current flowing when the holes are stored in the floating body of the transistor is larger than that flowing when no holes are stored. This phenomenon may be possible to distinguish whether the data “1” or “0” is stored in the unit cell.
The unit cell shown in FIG. 2 does not include a capacitor that has occupied a relatively large area in a conventional unit cell, thereby improving the integration of the semiconductor memory apparatus. However, it is difficult to prevent reduction of the amount of holes that the floating body of the FB transistor stores because of a leakage current that occurs at a source line (SL) junction or a bit line junction.
Generally, the active region (e.g., source/drain region) of the FB transistor, which is connected to the bit line or the source line (SL), includes impurities of high concentration in order to reduce resistance resulting from junction with metal layers. However, if the active region of the FB transistor is doped with impurities of high concentration, the amount of leakage current between the active region and the floating body may increase. As a result, the amount of holes stored in the floating body is dissipated as time goes by. Also, since the amount of the leakage current increases in proportion to temperature, data stored in the FB transistor of the unit cell is easily deleted under a high temperature. Finally, if the unit cell configured to have only the FB transistor without any capacitor, the semiconductor memory apparatus should perform a refresh operation for securing data more frequently; and performance of the semiconductor memory apparatus is deteriorated.